Multi-Level Cell (MLC) technology enables storage of multiple bits per memory cell by charging the floating gate of a transistor to different levels. For example, by dividing the voltage across each cell into four threshold voltage regions, each MLC memory cell is capable of storing two bits per memory cell. Therefore, MLC effectively reduces cell area as well as the die size for a given density.
However, during data read, it needs to perform more than one sensing operations to read data stored in a MLC memory cell. For example, given that the four threshold voltage regions of a MLC memory cell from low to high are corresponding to data “11”, “10”, “00” and “01”, respectively, it needs to perform twice data sensing operations to obtain the least significant bit stored in the MLC memory cell.
Therefore, there is a need for a memory sensing technology capable of effectively reducing the number of sensing operations when reading data from the memory.